1. Field of the Invention
The present invention relates to a semiconductor memory device. Particularly, the present invention relates to a dynamic type random access memory device including a plurality of memory cells each having a transfer gate transistor and a capacitor for storing a predetermined data.
2. Description of the Related Art
The conventional semiconductor memory device is provided with a plurality of word lines, a pair of dummy word lines, and a plurality of pairs of bit lines. Each pair of bit lines is connected to a terminal of each sense amplifier and is formed as a folded type, in which, for example, each pair of bit lines is arranged in parallel. A plurality of memory cells, each having one conductivity type transfer gate transistor and a capacitor for storing a predetermined data, are each connected between one of the word lines and one of the bit lines, and each of a plurality of dummy cells is connected between one of the dummy word lines and one of the bit lines.
When reading out the data stored in predetermined memory cells connected to a predetermined word line, a row decoder and word line driver supplies a predetermined selecting potential to a selected word line, and each transfer gate transistor connected to the selected word line is turned ON, and each potential of the bit lines connected to the turned-ON transfer gate transistors is varied to a different level in accordance with the data stored in the corresponding memory cell.
Simultaneously, the potential of each of the bit lines connected to a selected dummy word line via each of the dummy cells is set to a reference potential. Thus, the potential difference between the potential of each of the bit lines connected to the selected word line and the reference potential of the bit lines connected to the selected dummy word line is read out and amplified in the corresponding sense amplifier, and the output of the corresponding sense amplifier is supplied to corresponding data buses via predetermined transistors selected by a column decoder.
However, according to the above-mentioned conventional memory device having a plurality of word lines and a plurality of pairs of bit lines each formed as the folded type, the memory cells can be arranged only at every two intersections between the word lines and the bit lines. Therefore, in such a memory device, a problem arises in that any increase in the degree of integration of the memory cells arranged in the memory device is limited.